Today, the wind is very noisy. Shennan Avenue is full of traffic. In a building of the Science Park, Lei Bao, a siege lion, has done a very interesting project after solving the impedance test problem last time.

DDR4 simulation of a CPU chip. The design uses a single fly-by, one drag nine particle design. The running data rate was 3200Mbps.

The hand-drawn structure is as follows:

Look at its structure is ordinary, it must be a conventional CASE.

Leopao step by step, set up the stack, build the model, edit the code —–RUN, first extract a address signal, directly observe the eye diagram and waveform of DDR particle -U1 with the worst signal quality:



Although the eye map and waveform of U1 appear to be wobbly and have a small margin, there is still some distance from the level of the decision standard. So anyway, the answer is PASS.

As a simulation engineer, we always adhere to keep improving. How can we continue to optimize the signal quality? Leopard carefully checked the PCB, considered some of the conventional operation, there is not much room for optimization, it is decisive change to high-speed plate will there be an improvement?

Duang, soon changed to M6G plate, then set the cascade parameters, control the same impedance before, the signal topology remains unchanged, start the second round of simulation.

Continue to observe the eye map and waveform of U1.





The worst result of the point unexpectedly met the decision standard level?? You’re not coming over here!

The signal quality of FR4 plate with ordinary loss meets the requirements, but there are problems when replacing it with M6G plate with low loss.

Thunder Leopard scratched his head, lost in thought…

Combined with the theoretical knowledge of the study, Leopard on the two simulation environment was analyzed, a little bit.

The reasons are as follows:

Number one: chip drivers are too powerful

After a careful look at the IBIS model of the CPU, it is found that the rise time of the drive is very short and the rise edge is very steep. With the IBIS software, we can see the following picture when we look at the Rising offset of the address line call buffer:



Select 20% to 80% of the highest level, and the rise time in MIDDLE mode is only about 56ps. According to previous experience, the rise time of DDR4 signal is mostly between 100ps and 200ps, and the rise time around 56ps is relatively small, so the rise edge of the signal becomes steeper by comparison. That is, the more high-frequency components in the signal, the greater the reflection in the mismatched channel. The whole topology is dragged a lot of particles, which leads to the channel matching is OK, but the signal quality of the address line is not very good.

Second point: due to the replacement of plate, compared with ordinary FR4, the DF of M6G changed from 0.02 to 0.004

The loss value is smaller, and the attenuation degree of reflection is reduced, leading to some reflected energy will accumulate more than the ordinary plate, and the point of the worse signal will aggravate the deterioration. Simulation needs to take into account the factor of plate loss, which can attenuate the influence of rising edge and reflection. Therefore, the quality of DDR signal is not better if a better plate is changed. Different system environments may need to do detailed simulation to determine the signal quality.

The above is the problem of address line. In addition, there is no need to excessively consider this problem for data signal. The structure itself is one-to-one, with ODT (on-die Termination), there are few impedance mismatch points, and the topology is stable relative to address.