CMPXCHG is a Compare and Exchange instruction.

This article is based on the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2 (2A, 2B, 2C & 2D): Instruction Set Reference, A-Z), the function of CMPXCHG Instruction and its realization principle are summarized.

Instruction format

cmpxchg dest,src
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Compare the value in the AL, AX, EAX, or RAX register with the first operand, dest (target operand). If the two values are equal, the second SRC operand (source operand) is loaded into the target operand. If not, the target operand is loaded into the AL, AX, EAX, or RAX registers. The RAX register is only available in 64-bit mode.

This instruction can be used with the LOCK LOCK prefix to make the instruction execute atomically. To simplify the interface to the processor bus, the target operand receives a write cycle regardless of whether the comparison results are equal. If the comparison fails (unequal), the target operand will be written back (to the original value); Otherwise, the source operand is written to the destination operand. (The processor does not generate lock reads and does not generate lock writes.)

In 64-bit mode, the default operand size of this instruction is 32 bits. If the rex.r prefix is used, access to additional registers (R8-R15) is allowed. If you use the rex.w prefix, you can increase the operand size to 64 bits.

Take 64-bit mode as an example

CMPXCHG r/m32, r32
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Instruction description: Compare the values of register EAX and target operand R /m32 for equality. If the value is equal, set the ZF flag bit (set to 1), and save the value of register R32 to the operand R /m32, replacing the old value; If not, the ZF flag bit is cleared (set to 0) and the value of register R/M32 is loaded into register EAX, updating the value of EAX as the target operand.

R32: indicates the source operand and is used to temporarily store the new value. R /m32: indicates the target operand. If the instruction executes successfully, the value stored at its corresponding address will be replaced with the new value. EAX: A general-purpose register that temporarily stores old values for comparison with the target operands.

The detailed meaning of operand symbols

R32: represents a two-word (32-bit) general purpose register: EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI; Or if rex.r is used in 64-bit mode, it represents an available two-word register (R8D-R15D).

R/M32: represents a two-word (32-bit) general purpose register or memory operand for instructions with operand size of 32 bits. (such as using 32-bit registers, 32-bit memory units) Two-word general purpose registers are: EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI. When using rex.r in 64-bit mode, additional two-word registers (R8D-R15D) can be used.

Ia-32 architecture compatibility

This instruction is not supported on Intel processors prior to Intel486 processors.

Instruction pseudocode

TEMP := DEST // The value of the target operand is saved to TEMP
IF accumulator = TEMP // Compare the old value to the target value
  THEN // If equal, set ZF to 1 and save the new value to the target operand
    ZF := 1; // Set ZF to 1
    DEST := SRC; // Save the new value to the target operand
  ELSE // If not equal
    ZF := 0; // Clear ZF and set ZF to 0
    accumulator := TEMP; // Saves the value of the target operand to the accumulator
    DEST := TEMP; // Write the value of TEMP back to the target operand
FI;
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An Accumulator is AL, AX, EAX, or RAX, depending on whether a byte, one-word, two-word, or four-word comparison is performed. TEMP is used to hold the target operand temporarily. If the comparison fails, it is assigned to accumulator and written back to the target operand, DEST. ZF is a Zero Flag bit in the status register. If the result of the operation is Zero (0), set (1 or true), otherwise reset.

reference

The Intel documentation: software.intel.com/content/www…

The CMPXCHG instruction: www.felixcloutier.com/x86/cmpxchg

X86 register: www.cs.virginia.edu/~evans/cs21…

ZF marks: en.wikipedia.org/wiki/Zero_f…

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