This is the fifth day of my participation in the August More Text Challenge.

preface

This series full text in 10 w +, the full text is the note in his own dry, soft test involves many basic computer, data structure and algorithm analysis and programming ideas, development process and so on, not only suitable for soft people learn, also suit to broaden their knowledge to learn, each article will be focused bold processing, especially easy to fault point, Exam often test usually also easy to remember wrong, please look carefully! If you enjoyed this series, be sure to follow this column and even better, leave a little like!

Basic knowledge of computer system

Chapter comb

  1. Conversion between source code, inverse code and complement code

  2. Check code has error checking and error correction, and code distance is an important concept in check code, which refers to the number of at least binary differences between any two legal codes in an coding system

  3. Parity: To make the number of 1s in the code odd or even by adding parity codes to the code, thereby making the code spacing 2

  4. Hamming code * : If the data bit is set to N and the parity bit is set to K, n and 2^ K-1 must be greater than or equal to n+k

Cyclic redundancy check code (CRC) : r check bits are generated by generating polynomial bits K data bits, and the coding length is K + R. (XOR operation)

  1. The basic hardware of the computer system consists of five parts: arithmetic unit, controller, memory, input device and output device. Units such as arithmetic units and controllers are integrated together, collectively known as the central processing unit (CPU)

  2. CPU: The ALU has two main functions: performs all arithmetic operations such as +-** and add-on operations, performs all logical operations and runs logical tests.

  3. * Arithmetic unit also called arithmetic logic unit (ALU), accumulative register (AC) : Usually called accumulator, it is a general purpose register. The data buffer register (DR) uses DR to temporarily store an instruction or a data word read and written from memory storage, and to separate the data read and written at different times. State Condition register (PSW) : PSW holds various condition codes and contents created by arithmetic and logic instruction running or test results. It is mainly divided into status mark and control mark

Controller: Instruction register (IR), program counter (PC), Address register (AR), Instruction Decoder (ID)

  1. Hierarchical structure of the storage system: The three-tier storage structure is: Cache, main memory (MM) and auxiliary memory (external memory).

  2. Classified by location: Memory (main memory) : it is used to store programs and data required by the current operation with high speed and small capacity. External storage (auxiliary storage) : It is used to store the data that is not currently running. It has a large capacity but is slow.

Read/write memory: MEMORY that can both read and store data. Read only memory

Classification according to addressing mode: can be divided into random access memory (DRAM/RAM), sequential memory (SAM) and direct memory (DAM). (RAM random Access Memory) This kind of memory can store or read data from any memory location, and the time required to access any memory location is the same. (SAM Sequentially Access Memory) The time required to access data is dependent on where the data is stored. Tape is a typical sequential memory. DAM Direct Access Memory (DAM Direct Access Memory) an addressing mode between random and sequential access.

  1. Associative memory: a content-accessible memory that works by comparing data and a key for a part of the data to each location in memory to find all data in memory that is identical to the key.

Cache is a high-speed storage subsystem between CPU and main memory. The main purpose of using cache is to improve the average access speed of memory, so that the speed of memory and the speed of CPU match.

The existence of the Cache is transparent to the programmer, and its address shuffling and block replacement algorithms are implemented by hardware. It is usually integrated into the CPU and is characterized by small capacity, high speed and high cost. It consists of two parts: control and storage. Storage section A section of replication information used to store main storage. The function of the control part is to determine whether the information to be accessed by the CPU exists in the Cache memory, if there is a hit, otherwise vice versa.

  1. There are three methods of address image: direct image (advantage: simple address transformation, disadvantage: poor flexibility), full association image (advantage: location is not limited, very flexible, disadvantage: complex transformation, slow speed), group association image (the first two compromise).

Replacement algorithm: Random replacement (RAND), First in, first out (FIFO), Least Recently used (LRU), Optimized replacement (OPT)

**Cache performance analysis: Equivalent time = Hit ratio storage time (period) + (1- Hit ratio) main memory access time

  1. Virtual memory is a storage system composed of main storage, auxiliary storage, storage management unit and storage management software in the operating system

Data transfer between CPU and peripheral:

  • 1, direct program control {unconditional transmission mode, program query mode (disadvantages: reduced CPU efficiency, can not make real-time response to external emergencies. Advantages: Easy to understand, easy to work)}
  • 2, interrupt mode (CPU does not need to wait, do not need to query THE IO state, can get out to deal with other tasks, so improve the system efficiency) {interrupt priority control, interrupt processing method}!
  • 3, * Direct memory access (DMA) is the direct transfer of data between memory and IO device, that is, in the process of transferring a data block between memory and IO device, without any interference of CPU, is a completely DMA hardware to complete THE IO operation mode.
  • 4, output and input processors {byte multiplexing, selective transfer, array multiplexing}

System bus: ISA bus, EISA bus,PCI bus (data, address, control bus)

  1. In the single-machine system, the bus system of the three-bus structure computer is composed of system bus, memory bus and IO bus. The system bus is used to transfer address, data and control information between CPU and memory.

  2. Instruction system: 1 addressing mode (immediate addressing, register addressing, direct addressing, register indirect addressing, register relative addressing, base plus variant addressing, relative base plus variant addressing)

  3. CISC and RISC: CISC (Complex Instruction set computer, large quantity, large frequency difference and long development cycle) and RISC (reduced Instruction set computer) Improve execution speed, optimize compiler)

Instruction control mode: sequential mode, overlapping mode, flow mode

Method of flow: By “trial by analysis” (three steps are executed in different locations)

  1. Computer reliability model: serial system: reliability is R=R1R2…. Rn failure rate is 1-reliability, parallel system: reliability is R= (1-R1) (1-R2)…… (1-RN) {Improve computer reliability: improve the quality of components, improve processing technology and process structure, and develop fault-tolerant technology}

  2. Performance evaluation of computer systems: performance evaluation commonly used methods: clock frequency, instruction execution speed, equivalent instruction speed method, data processing rate method (PDR), core program method

  3. Benchmarks: Currently, it’s generally accepted that these are better performance methods (four common ones: integer, floating point, SPEC, and TPC benchmarks).

Easy to make mistakes and knowledge integration

  • Master the conversion of base 16, base 2, base 8 and base 10

  • 2^10=1024 2^18=256k 2^15=32k

  • Dynamic Random Access Memory (DRAM) is the most common system memory. SRAM (static access functional memory, which can hold data stored within it without needing to refresh the circuit and is used as a Cache accessor, or Cache)

  • Fetching refers to the cycle of fetching instructions, the execution cycle of fetching data.

  • VLIW is the abbreviation of very long Instruction word (very long Instruction word). It is a very long instruction combination, which connects many instructions together to increase the speed of operation.

  • Shift operators: Shift numbers on a binary basis. According to the direction of translation and the rule of filling number, it can be divided into three types: << (left move), >> (signed right move), >>> (unsigned right move). As long as there is no overflow, for both positive and negative numbers, a shift to the left equals2, n to the left is equal toTwo to the NTH power, to the right and vice versa.

  • The bus cycle usually refers to the time it takes a CPU to complete a memory or IO port access operation.

  • Floating point number: N=2^e*F e is the order code, determines the range of values that floating point number can represent; F is the mantissa, which determines the numerical precision that a floating point number can represent.

  • Floating point: When the machine word length is N, the complement and shift of the fixed point can represent 2^n numbers, while the source and inverse can only represent 2^ n-1 numbers (0 takes up two codes).

  • If the instructions are executed in sequence, the execution time of n items is :(refers to the time + analysis time + execution time) *n

  • A machine word length is N, the highest bit is a sign bit, the maximum number of fixed points is 2^ n-1-1

  • DMA control mode is to directly establish a data path between main memory and peripherals for data exchange processing