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CPU working modes include real mode, protected mode, and long mode

Real mode

In this mode, real instructions are run and the real functions of the instructions are directly executed without distinguishing the actions of the instructions. The address sent to memory is real, no limit to any address sent to memory.

The relevant registers in x86 mode are as follows:

Now we need to consider how to access memory in real mode. The general memory address is shifted four places left by the segment register (CS), and a value or constant in a general purpose register is added to form an address from which memory is accessed.

It’s important to note that,

  • The code segment is determined by CS and IP
  • The stack segment is determined by SS and SP

Interrupt implementation in real mode: save the CS and IP registers, then load the new CS and IP registers. Interrupts can occur in a number of ways:

  • The interrupt controller sends an electronic signal to the CPU, to which the CPU responds. The interrupt controller then sends the interrupt number to the CPU, which is a hardware interrupt

  • The CPU executes the INT instruction, which is followed by a constant, which is the soft interrupt signal,

To implement interrupts, you need to place an interrupt direction table in memory whose address and length are pointed to by the CPU specific register IDTR. In real mode, an entry in a table consists of a code segment address and an in-segment offset.

Protected mode

Protected mode expands the bit width of the general purpose register by adding control registers and segment registers compared to real mode, so all the general purpose registers are 32 bits, and can also use a single lower 16 bits, which can be split into two 8-bit registers.

Protection mode privilege level

To distinguish which instructions and which resources can be accessed, the CPU implements a number of privilege levels. Four levels, R0 to R3. R0 can execute all instructions, R1, R2, R3 in descending order.

Protect the mode segment descriptor

Because CPU expansion causes 32-bit segment base addresses and in-segment offsets, among other things, the 16-bit segment register will not fit. Encapsulate the information describing a segment into a segment descriptor in a specific format and store it in memory

Multiple segment descriptors form a global segment descriptor table in memory, whose base address and length are indicated by the CPU and GDTR registers.