1 Timing design

2 Serial port receiving module (serial conversion and combination)

2.1 Module Design

2.2 Serial Port Start Detection (High and Low Jump)

  • The start bit is captured by detecting the falling edge of the serial port receiver UARt_rxD. Once the start bit is detected, output a clock cycle pulse start_flag and enter the serial port reception process. The serial port receiving status is marked by RX_Flag. A high RX_flag indicates that the serial port receiving process is in progress. At this time, the system clock counter CLK_CNT and the receiving data counter RX_CNT are started.

2.3 Timing Setting

    1. Duration of serial port transmission :(1/15200)
    1. Serial port transmission bit need FPGA system clock count value :(1/15200)/(1/50000000)

    1. When the pulse signal start_flag arrives, it enters the receiving process and counts to 9 bits to clear rX_Flag

    1. Register the number of UART receive ports according to the receive data counter

    1. Uart_done signal is given after the data is received, and the received data is stored and output

3 Serial port sending module (parallel conversion)

3.1 Module Design

3.2 Serial Port Sending Start Detection (High and Low Jump)

3.3 Timing Setting

  • When the pulse signal EN_flag arrives, the data to be sent is stored and the sending process begins
  • After entering the sending process, start the system clock counter
  • Assign values to the UART sender according to the send data counter