Hello, everybody. I’m back at last! As soon as I submitted my big paper on 19th, I was arrested and went on a business trip, which lasted for a whole week. On the evening of 26th, I came back to school. The pigeon hasn’t been refreshed in a long time. Today, I updated a written interview topic about Arm. The content of the article has been synchronously updated on Github.

[TOC]

ARM architecture and architecture

hardware

NAND FLASH vs. NOR FLASH?

The difference between

category NOR NAND
read Like accessing SRAM, data can be accessed randomly at any address; For example, unsealed short *pwAddr = (unsealed short *)0x02; unisignded short wVal; wVal = *pwAddr Fast, with strict timing requirements, need to read data through a function, first send read command -> send address -> judge whether Nandflash is ready -> read a page of data read command, send address, judge state, read data are realized by operating registers, such as data register NFDATA
write Slow, need to erase before writing, because write can only be 1->0, erase can make 0->1 Quick, erase before you write, because write can only be 1->0, erase makes 0->1
erase Very slow (5S) Fast (ms)
XIP Code can be run directly on NOR FLASH NO
reliability Relatively high, the bit inversion ratio is less than 10% of NAND FLASH Relatively low, bit inversion is more common, must have a check measure
interface As with the RAM interface, the address and data bus are separate The I/O interface
Erasable number of times 10000 ~ 100000 100000 ~ 1000000
capacity Small, 1 MB to 32 MB Big, 16 MB to 512 MB
The main purpose Often used to save code and critical data Used to save data
The price high low

Note: the 0 address of nandflash and norflash do not conflict. Norflash uses the BANK address, while nandFlash does not use the BANK address. Its 0 address is internal.

The same

1 Always erase before writing, because write can only make 1->0, and erase is to change all bits to 1
2 Erase units are all in blocks

CPU,MPU,MCU,SOC,SOPC connections and differences?

1. The Central Processing Unit (CPU) is the computing and control core of a computer. The CPU consists of an arithmetic unit, a controller, and a register, and a bus that implements the data, control, and state that are connected between them. Almost all cpus operate in four stages: Fetch, Decode, Execute, and Writeback. The CPU takes instructions from memory or cache, places them in an instruction register, interprets the instructions, and executes the instructions. Computer programmability mainly refers to the programming of the CPU.

2. A Micro Processor Unit (MPU), or microprocessor (not microcontroller), usually stands for a powerful CPU (think of it as an enhanced VERSION of the CPU), but not a chip designed for any existing specific computing purpose. Such chips tend to be the core CPUS of personal computers and high-end workstations. The most common microprocessors are Motorola’s 68K family and Intel’s X86 family.

3.MCU(Micro Control Unit), called microcontroller, refers to the emergence and development of large-scale integrated circuit, the COMPUTER CPU, RAM, ROM, timing counter and a variety of I/O interface integrated on a chip, the formation of chip level chips, such as 51, AVR chips, In addition to the CPU, internal RAM,ROM, can directly add simple peripheral devices (resistance, capacitor) can run the code, and MPU such as x86, ARM these can not directly put the code, it is only the enhanced version of the CPU, so have to add RAM,ROM.

The main difference with the MCU MPU is the ability to run code directly. The MCU has an internal RAM ROM, while the MPU is an enhanced VERSION of the CPU that requires an external RAM ROM to run code.

4.SOC (System on Chip) refers to the System on Chip, MCU is only Chip level Chip, while SOC is system-level Chip, it is not only MCU (51, AVR) with built-in RAM,ROM at the same time as MPU (ARM) as powerful, not only put simple code, can put system-level code, That is to say, it can run an operating system (which we will consider a combination of MCU integration and MPU processing power).

SOPC (System On a Programmable Chip) (FPGA is one of them), the hardware configuration of the above four points is fixed, that is to say 51 single Chip is 51 single Chip and cannot be changed into AVR, while AVR is AVR not 51 single Chip. Their hardware is a one-time mask molding, the only thing that can be changed is the software configuration, to put it bluntly is to change the code, it was originally running water lamp, change the code, become digital tube, while SOPC is the hardware configuration, software configuration can be changed, the software configuration is the same as above, nothing to say, as for the hardware, Can build yourself that is to say, this chip is to construct their own, the chip we call “white”, what chip are not, please download in hardware configuration information, and he is the corresponding chip, can let him become a 51, also can be avr, even the arm, is based on the SOC and SOPC, so he is also a system level chip, So remember to add peripheral ROM, RAM and so on when turning it into ARM or MPU.

What is cross-compilation?

A compiler that runs in one computer environment and produces code that runs in another is said to support cross-compilation. This compilation process is called cross-compilation. Simply put, it means generating executable code on one platform for another.

What needs to be noted here is that the so-called platform actually contains two concepts: Architecture and OperatingSystem. The same architecture can run different operating systems; Similarly, the same operating system can run on different architectures. For example, what is often referred to as the x86 Linux platform is actually the collective name of the Intel x86 architecture and Linux for x86 operating system; The x86 WinNT platform is actually short for Intel x86 architecture and Windows NT for x86 operating system.

Why cross-compile?

Sometimes it is because the compiler we want is not allowed or can’t be installed on the destination platform and we need some features of the compiler. Sometimes the target platform is too resource-poor to run the compiler we need. Sometimes it’s because the destination platform hasn’t been built, or even an operating system, to run a compiler at all.

Describe the difference between embedded ROM – based operation and RAM – based operation.

Based on the RAM

  1. The code of the hard disk and other media needs to be loaded into RAM first, and there is usually relocation operation during the loading process.
  2. Faster than ROM based, less RAM available than ROM based, because all code, data must be stored in RAM.

Based on the ROM

  1. It is slower than RAM-based because there is a process of moving variables, parts of code, etc from memory (hard disk, Flash) to RAM.

  2. More RAM resources are available than ram-based;

ARM processor

What are harvard structures and Von Neumann structures?

define

Von Neumann structure uses unified instruction and data addressing, using the same bus transmission, CPU read instruction and data operations cannot overlap.

The Harvard architecture allows instruction and data to be addressed independently, using two separate buses for transmission, and the CPU’s operation of reading instruction and data can overlap.

The pros and cons

Von Neumann structure is mainly used in the field of general purpose computer, which requires frequent modification of the code and data in the memory. Unified addressing is beneficial to saving resources.

Harvard structure is mainly used in embedded computer, the program is solidified in the hardware, has high reliability, operation speed and large throughput.

What is ARM pipelining technology?

Pipelining technology has become one of the most important technologies in microprocessor design because it can shorten the program execution time and improve the efficiency and throughput of processor core through the parallel work of multiple functional components. The ARM7 processor core uses the von Neumann architecture of the typical three-stage pipeline, while the ARM9 family uses the Harvard architecture based on the five-stage pipeline. By adding pipeline levels, the logic of pipeline levels is simplified and the processor performance is further improved.

PC represents the program counter, and the pipeline uses three stages, so the instruction is divided into three stages: 1. To load (an instruction from storage); 2. Decoding (identifying instructions to be executed); 3. Execute (process the instruction and write the result back to the register). R15 (PC) always points to an instruction that is “pointing”, not to an instruction that is “executing” or “decoding”. In general, people have a convention to refer to the “executing instruction as a reference point”, called the current first instruction, so the PC always points to the third instruction. When in ARM state, each instruction is 4 bytes long, so PC always points to the address of the instruction plus 8 bytes, that is: PC value = current program execution position +8;

The ARM instruction is a three-level pipeline, fetching, translating, executing and executing simultaneously. Now the PC points to the address that is fetching (the next instruction), so the CPU is translating the address of the instruction is PC-4 (assuming that in the ARM state, an instruction takes up 4 bytes), and the CPU is executing the address of the instruction is PC-8. That is, there is a difference of 8 between the address the PC points to and the address of the instruction being executed.

When an interrupt occurs, the address of the PC is saved (PC-8+4 = the address of the next instruction in PC-4).

So you know that if you return PC, then one of the instructions is not executed, so use SUB PC LR-irq #4.

How many modes does ARM work?

  1. User mode (USR)

    User mode is the working mode of the user program, it runs in the user mode of the operating system, it does not have the permission to operate other hardware resources, can only perform processing of their own data, can not switch to other modes, to

    Accessing hardware resources or switching to other modes can only be done through soft interrupts or exceptions.

  2. System Mode (SYS)

    System mode is privileged mode and is not restricted by user mode. User mode and system mode share a set of registers, the operating system in this mode can easily access the user mode register, and the operating system

    Privileged tasks can use this pattern to access controlled resources.

    Note: The user mode and the system mode use the same Register and do not have the Saved Program Statement Register (SPSR). However, the system mode has higher permissions than the user mode and can access all system resources.

  3. General Interrupt Mode (IRQ)

    The common interrupt mode is also called the common interrupt mode. It is used to process common interrupt requests. The privileged mode is automatically entered after the hardware generates interrupt signals and allows free access to system hardware resources.

  4. Fast interrupt mode (FIQ) Compared with the general interrupt mode, the fast interrupt mode is used to process the interrupt requests with urgent time requirements. It is mainly used in high-speed data transmission and channel processing. Fast interrupts have many (R8~R14) special registers of their own. In the event of an interrupt, using their own registers avoids saving and restoring some registers. If registers other than its own physical registers are used in the exception interrupt handler, the exception interrupt handler must save and restore those registers.)

  5. Management mode (SVC) The management mode is the default mode after the CPU is powered on. Therefore, this mode is mainly used for system initialization and soft interrupt processing. When a user program in user mode requests the use of hardware resources, it enters the mode through software interrupts.

    Note: The system enters SVC mode when the system is reset, powered on, or soft interrupted.

  6. ABT: The ABT mode is used to support virtual memory or storage protection. When a user program accesses an invalid segment that does not have access permission, it enters this mode.

  7. Undefined mode (UND) : Undefined mode is used to support software emulation of a hardware coprocessor. When the CPU fails to recognize the operation of an instruction during the decoding phase, it enters undefined mode.

  1. In addition to user mode, the other six modes are called privilege mode. The privilege mode is defined as having the following rights:

A. MRS (place the contents of the status register in the general register);

B. MSR (puts the contents of the general register into the status register).

Since the contents in the status register cannot be changed, the task of “modifying the status register” can be completed by copying the contents to the general register, modifying the contents in the general register, and then copying the contents in the general register to the state register.

  1. Apart from the system pattern, the remaining six patterns are collectively referred to as the exception pattern.

How many 32-bit registers does Arm have?

The ARM processor has 37 registers. It contains 31 general purpose registers and 6 state registers.

What’s the difference between Arm2440 and 6410?

  1. The main frequency is different. So 2,440 is 400 meters. 6410 is 533/667m;

  2. Processor versions are different: 2440 is arm920T core, 6410 is arm1176ZJF core.

  3. The 6410 is much better at video processing than the 2440. Internal video decoders, including MPEG4 and other video formats;

  4. 6410 supports hard decoding and encoding of WMV9, XVID, MPEG4, H264 and other formats.

  5. 6410 has many and many extension interfaces, such as TV-out, CF card and S-video output, etc.

  6. Spi, serial port, SD interface is also richer than those two;

  7. 6410 uses DDR memory controller; 2440 uses SDRam memory controller;

  8. 6410 is dual-bus architecture, one for memory bus, one for Flash bus;

  9. The 6410 has more flexible boot modes, including SD, Nand Flash, Nor Flash and OneFlash, etc.

  10. The 6410 Nand Flash supports SLC and MLC architectures, which greatly expands the storage space.

  11. 6410 is dual-bus architecture, one for memory bus, one for Flash bus;

  12. 6410 has 8 DMA channels, including LCD, UART, Camera and other dedicated DMA channels;

  13. The 6410 also supports 2D and 3D graphics acceleration;

How many types of ARM instruction sets are there?

Class 2, Thumb instruction set, ARM instruction set respectively. The ARM instruction is 32 bits long and the Thumb instruction is 16 bits long. This feature enables ARM to execute both 16-bit and 32-bit instructions, enhancing the capabilities of the ARM kernel.

General purpose registers include R0 ~ R15, which can be divided into three categories?

General purpose registers include R0-R15, which can be divided into 3 classes:

  1. Ungrouped registers R0-R7

    In all operating modes, the ungrouped registers point to the same physical register, and they are not used by the system for special purposes. Therefore, the data in the register may be damaged because different processors use the same physical register in the abnormal mode conversion during interrupt or exception processing.

  2. Block registers R8-R14

    For block registers, the physical registers they access each time are related to the current processor operating mode.

    R13 is commonly used to store the stack pointer, and users can use other registers to store the stack pointer, but under the Thumb instruction set, some instructions mandate R13 to store the stack pointer.

    R14 is called the Link Register (LR, Link Register). When the subroutine is executed, R14 can get the backup of R15 (PC). After the subroutine is executed, the value of R14 is copied back to PC, that is, R14 is used to save the return address.

  3. Program Counter PC (R15)

    Register R15 is used as program counter (PC). In ARM state, bit [1:0] is 0, bit [31:2] is used to save PC. In the Thumb state, bit [0] is 0, and bit [31:1] is used to hold the PC.

How many operating states does an Arm processor have?

From a programming point of view, ARM microprocessors generally operate in two states, ARM and Thumb, and can switch between the two states.

  1. ARM state: This is where the processor executes 32-bit word alignment ARM instructions and most of the work is in this state.

  2. Thumb state: This is when the processor executes 16-bit halfword-aligned Thumb instructions.

In ARM systems, how are parameters passed when a function is called?

Parameters less than or equal to 4 are passed through the R0-R3 register, and parameters greater than 4 are passed through the stack.

Why is the memory start address of 2440 0x30000000?

The S3C2440 processor has eight fixed memory blocks, only two of which can be used as memory banks such as ROM,SRAM and SDRAM. The details are shown in the following figure.

What are the three classes of ARM coprocessor instructions and describe their functions?

ARM coprocessor instructions include the following three classes:

  1. Data processing operations used by the ARM processor to initialize the ARM coprocessor.

  2. Data transfer operations between the registers of the ARM processor and the registers of the ARM coprocessor.

  3. Used to transfer data between registers and memory units of the ARM coprocessor.

What is PLL (Phase-locked Loop)?

Simply put, the input clock exists as a “reference source.” The PLL is not intended to simply produce the same frequency and confidence signal, but is generally integrated into some kind of “frequency synthesis circuit” to produce a different frequency, but a phase-locked signal.

For example, A reference crystal oscillator of 10Mhz, frequency synthesizer A uses this reference source to generate A 900Mhz clock, and frequency synthesizer B generates A 1Ghz clock. Although the frequencies of the two channels are different, they are still homologous signals because they use the same reference source. On the other hand, if they have different sources, they cannot be the same even if they have the same frequency, because no two clocks in the world can be exactly the same, and there is always a slight frequency difference that causes the phase to drift. In many practical applications, there are occasions requiring homologous clock, so PLL is widely used. Another derivative of PLL is coherent demodulation, which you can look up for yourself.

Interrupts and exceptions

What is the difference between interrupts and exceptions?

An interrupt is when an electrical signal generated by external hardware enters the INTERRUPT pin of the CPU and interrupts the operation of the CPU.

An exception refers to an event that must be handled when the software is running. The CPU automatically generates a trap to interrupt the CPU. Exceptions must be handled in sync with the processor’s clock. In fact, exceptions are also called sync interrupts, which are generated when the processor executes an incorrect instruction due to a compilation error, or when a special error occurs during execution that must be handled by the kernel.

What is the difference between interrupts and DMA?

DMA: A hardware mechanism for two-way data transfer between peripherals and system memory without the involvement of the CPU. Using DMA, the system CPU can be freed from the actual I/O data transfer process, thus greatly improving system throughput.

Interrupt: When an emergency occurs during the execution of the program, the CPU must suspend the execution of the current program and switch to processing the emergency. After the processing is complete, the CPU returns to the position where the source program is interrupted and continues to execute the program.

So the difference between interrupts and DMA is that DMA does not require CPU input, while interrupts do.

Can interrupts sleep? Why? Can you sleep in the lower part?

  1. Process switching should not occur while interrupt processing. Because in the interrupt context, the only interrupt that can interrupt the current interrupt handler is the higher-priority interrupt, which will not be interrupted by the process. If it sleeps in the interrupt context, there is no way to wake it up because all wake_up_xxx is specific to a process, and in the interrupt context there is no process and no task_struct (the same for Softirq and Tasklets). So if it does sleep, for example by calling a routine that causes blocking, the kernel will almost certainly die.

  2. Schedule () saves the current process context (the value of the CPU registers, the state of the process, and the contents of the stack) when switching processes so that the process can be resumed later. After an interrupt occurs, the kernel first saves the context of the currently interrupted process (restored after the interrupt handler is called).

    But in interrupt handlers, the VALUE of the CPU register must have changed (the most important program counters PC, stack SP, etc.). If schedule() is called at this point because of a sleep or blocking operation, the saved process context is not the current process context. Therefore, schedule() cannot be called in an interrupt handler.

  3. 2.4 The schedule() function itself checks whether it is in an interrupt context when it enters:

if(unlikely(in_interrupt()))
BUG();
Copy the code

Therefore, the result of forcing a call to schedule() is a kernel BUG, but the implementation of schedule() in 2.6.18 does not have this statement.

  1. The interrupt handler uses the kernel stack of the interrupted process, but it doesn’t affect it at all, because when the handler is done using it, it will completely clean up that part of the stack and restore it to where it was before the interrupt.

  2. The kernel is not preemptible in interrupt context. Therefore, if you hibernate, the kernel must hang.

What is the response execution process for an interrupt?

Interrupt response process: CPU accept interrupt -> save interrupt context jump to interrupt processing process -> execute interrupt upper half -> execute interrupt lower half -> restore interrupt context.

What steps does the ARM microprocessor perform when an exception occurs?

  1. The address of the next instruction is put into the corresponding connection register LR so that the program can restart execution from the correct position when handling an exception return. If the exception is entered from the ARM state, the LR register stores the address of the next instruction (current PC+4 or PC+8, depending on the type of exception). If the exception comes in from the Thumb state, the offset of the current PC is saved in the LR register so that the exception handler does not need to determine from what state the exception came in. For example: in software interrupt exception SWI, instruction MOV PC, R14_svc always returns to the next instruction, regardless of whether SWI is executed in ARM state or Thumb state.
  2. Copy the CPSR to the corresponding SPSR.
  3. The CPSR running mode bit is forcibly set based on the exception type.
  4. Force the PC to jump to the appropriate exception handler by fetching the next instruction from the relevant exception vector address.

What should I pay attention to when writing an interrupt service? What do you do if you have to do more after an interrupt occurs?

  1. Write an interrupt service routine to be quick in and quick out. In the interrupt service routine, collect information as quickly as possible, including hardware information, and exit the interrupt. To do other things, use work queues or tasklets. That is to interrupt the upper and lower parts.

  2. There must be no blocking operations in interrupt service routines. Because the interrupt is completely CPU-intensive (that is, there is no kernel scheduling), the interrupt is blocked and other processes are unable to operate.

  3. Interrupt service routines pay attention to the return value and use the macro defined by the operating system as the return value, not their own.

  4. If you have a lot of work to do, put those tasks in the second half (tasklets, wait queues, etc.).

Why is FIQ faster than IRQ?

  1. R8,R9,R10,R11, and R12 have more banked registers than R8,R9,R10,R11, and R12. This means that in ARM’s IRQ mode, The interrupt handler saves the R8 to R12 registers by itself, and then restores these registers when it exits the interrupt processing. In FIQ mode, because these registers have banked registers, the CPU automatically saves these values to the Banked register during mode switch, and restores them automatically when it exits FIQ mode. So FIQ is faster than IRQ. Don’t underestimate these registers. When ARM is compiled, if your FIQ interrupt handler has enough independent registers to run, it won’t stack the general purpose registers, which saves some time.

  2. FIQ has a higher priority than IRQ. If FIQ and IRQ are generated at the same time, FIQ is processed first.

  3. In Symbian system, when THE CPU is in FIQ mode processing FIQ interrupt process, prefetch instruction exception, undefined instruction exception, software interrupt is prohibited, all the interrupt is shielded. So FIQ executes quickly and is not interrupted by other exceptions or interrupts, so it is faster than IRQ again. IRQ is different. If an FIQ interrupt request comes in, the IRQ interrupt handler will be interrupted. ARM switches to FIQ mode to execute the FIQ interrupt, so FIQ is much faster than IRQ.

  4. In addition, the FIQ entry address is 0x1c, and IRQ entry address is 0x18. Wrote a complete assembly system are understand this difference, can put an instruction only 18, in order not to conflict with 1 c in FIQ, this place can only jump, and FIQ, 1 c later without any interruption to the scale, so that we can put directly on the 1 c FIQ interrupt handlers, because of the limit to jump, at least a jump instruction.

Which is more efficient, interrupt or polling? How to decide whether to implement drivers in interrupt mode or in polling mode?

Interrupt is the CPU in a passive state to receive the device’s signal, and polling is the CPU to actively query whether the device has a request.

Everything has two sides, so efficiency can not simply say that the efficiency is high. If the requesting device is a device that frequently requests CPU, or a network device that has a large number of data requests, polling is more efficient than interrupting. If it is a generic device and the device requests the CPU less frequently, the interrupt efficiency is higher. It depends on the frequency of requests.

Communication protocol

What are asynchronous and synchronous transmission?

Asynchronous transmission: A typical byte – based input/output. Data is transmitted one byte at a time, and the transmission speed is low.

Synchronous transmission: requires external clock signals to communicate, is the combination of data bytes sent together, called frames, its transmission speed is faster than asynchronous transmission.

What is the difference between RS232 and RS485 communication interface?

  1. The transmission mode is different. RS232 adopts unbalanced transmission mode, namely the so-called single – end communication. And RS485 uses balanced transmission, namely differential transmission.

  2. Transmission distance is different. RS232 is suitable for communication between local devices, and the transmission distance is generally less than 20 meters. The transmission distance of RS485 is tens of meters to thousands of meters.

  3. Number of devices. RS232 only allows one-to-one communication, while the RS485 interface on the bus is allowed to connect up to 128 transceivers.

  4. Connection mode. RS232, the provision of level to represent data, so the line is a single line, with two lines to achieve the purpose of full duplex; And RS485, the use of differential level data, therefore, must use two lines to achieve the basic requirements of transmission data, to achieve full duplex, must use 4 lines.

Summary: In a sense, it can be said that there is only current on the line, RS232/RS485 defines the current in what kind of line flow and flow style.

SPI agreement

The application of SPI

SPI(Serial Peripheral Interface) protocol is a communication protocol proposed by MOTOROLA, that is, Serial Peripheral Interface, which is a high-speed full-duplex communication bus. SPI bus system is a synchronous serial peripheral interface, which enables MCU to communicate with various peripheral devices in a serial way to exchange information. The SPI bus can be directly connected to A variety of standard peripherals produced by various manufacturers, including FLASH, RAM, network controller, LCD display driver, A/D converter and MCU.

interface

  1. MOSI (Master Output， Slave Input)

    Master output/slave input pins. The data of the host is output through this signal line, and the slave machine reads the data sent by the host through this signal line, that is, the direction of the data on this line is from the host to the slave machine.

  2. MISO(Master Input, Slave Output)

    Master device input/slave device output pins. The host reads data from the signal cable, and the slave data is output from the signal cable to the host. That is, the direction of data on this line is from the machine to the host.

  3. SCLK (Serial Clock)

    Clock signal line for communication data synchronization. It is generated by the communication host and determines the communication rate. Different devices support different maximum clock frequency, for example, the SPI clock frequency of STM32 is FPCLK /2. When two devices communicate, the communication rate is limited to low-speed devices.

  4. SS( Slave Select)

    Select a signal cable from the device, often called chip select signal cable, also known as NSS, CS, the following is denoted by NSS. When multiple SPI slave devices are connected to the SPI host, the other signal lines of the device, SCK, MOSI and MISO, are simultaneously connected to the same SPI bus, that is, no matter how many slave devices there are, they only use these three buses. And each slave device has an independent NSS signal line, the signal line is exclusive to a pin of the host, that is, how many slave devices, how many pieces choose the signal line.

    I2C protocol through the device address to address, select a device on the bus and communicate with it; SPI protocol does not have device address, it uses NSS signal line to address, when the host wants to select a slave device, set the NSS signal line of the slave device to low level, the slave device will be selected, that is, the chip selection is effective, then the host starts SPI communication with the selected slave device. Therefore, SPI communication starts with the signal that the NSS line is set low and ends with the signal that the NSS line is raised.

The protocol layer

Common connection modes between SPI communication devices are shown in the following figure:

The communication sequence of SPI communication is shown in the figure below:

  1. The start and stop signals of communication

    At label 1 of the figure, the NSS signal line changes from high to low, which is the starting signal of SPI communication. NSS is an exclusive signal line for each slave machine. When the slave machine detects the start signal on its own NSS line, it knows that it is selected by the host and starts to prepare for communication with the host machine. At the label  in the figure, the NSS signal changes from low to high, which is the stop signal of SPI communication, indicating that the communication ends and the selected state of the slave machine is cancelled.

  2. Data validity

    SPI uses MOSI and MISO signal lines for data transmission and SCK signal lines for data synchronization. MOSI and MISO data lines transmit one bit of data per clock cycle of SCK, and data input and output are carried out simultaneously. MSB first (high first) or LSB first (low first) is not mandatory for data transmission, but the MSB first (high first) mode shown in the figure above is generally used to ensure that the same protocol is used between the two SPI communication devices.

    At label 2345 in the observation figure, MOSI and MISO data varied during the rising edge of SCK and were sampled during the falling edge of SCK. That is, at the falling edge of SCK, the data of MOSI and MISO are valid. When the current is high, it means data “1”; when the current is low, it means data “0”. At other times, the data is invalid, and MOSI and MISO prepare the data for the next presentation.

    Each SPI data transfer can be 8 – or 16-bit units. There is no limit on the number of units per transfer.

  3. CPOL /CPHA and communication modes

    The timing shown in the diagram above is only one of the four communication modes in SPI. The main differences between them are the clock state of SCK when the bus is idle and the time of data sampling. For convenience, the concepts of clock polarity CPOL and clock phase CPHA are introduced here.

    Clock polarity CPOL refers to the level signal of the SCK signal line when the SPI communication device is in idle state (that is, before THE SPI communication starts and the NSS line is in high power state). When CPOL=0, SCK is low in idle state, and vice versa when CPOL=1.

    CPHA is the time at which exponential data is sampled. When CPHA=0, signals on the MOSI or MISO data line will be sampled on the “odd edge” of the SCK clock line. When CPHA=1, the data line is sampled at the “even edge” of the SCK.

IIC agreement

Introduction to the

IIC protocol is a serial bus composed of data line SDA and clock SCL, which can send and receive data. It is a half duplex communication mode of multiple hosts

Each device attached to the bus has a unique address. The bit speed can reach 100kbit/s in standard mode, 400kbit/s in fast mode, and 3.4Mbit/s in high-speed mode.

I2C bus system structure is as follows:

Introduction to I2C timing sequence

1. Idle state

When SDA and SCL signal lines on the bus are in high level at the same time, it is in idle state. As shown in the hardware diagram above, when we do not transmit data, SDA and SCL are pulled up by pull-up resistance, that is, they enter idle state

2. Initial signal

When SCL is high, SDA jumps from high to low. Is the starting signal of the bus, which can only be initiated by the host and can be started in idle state, as shown below:

3. Stop signal

When SCL is high, SDA jumps from low to high. Is the ** stop signal of the bus,** means that the data has been transmitted, as shown below:

4. Data transmission Format When the start signal is sent, the data transmission format is as follows:

When the SCL is high, the SDA data value is obtained, where the SDA data must be stable (it becomes a start/stop signal if the SDA is unstable).

When SCL is low, it is the level change state of SDA.

If the master and slave need to complete other functions (such as an interrupt) during data transmission, they can actively pull down the SCL to make the I2C enter the waiting state, release the SCL until the end of processing, and the data transmission will continue

5. Reply signal ACK

The data on the I2C bus are all 8-bit data (bytes). When 8 data are sent, the sender will release THE SDA data during the 9th clock pulse. When the receiver receives the byte successfully, it will output an ACK response signal. Represents a valid reply signal ACK

PS: If the host is the receiver, after receiving the last byte, the host can directly send the stop signal to end the transmission.

When the slave machine is the receiver and does not send an ACK, it indicates that the slave machine may be busy with something else, or the address signal does not match and the multi-host transmission is not supported. The host can send a stop signal and send a start signal again to start a new transmission.

6. Complete data transmission

As shown in the figure below, after sending the start signal, an 8-bit device address is sent, with the 8th bit being the read/write flag to the device, followed by the data, until the sending stop signal terminates.

PS: When we first do a read operation, and then want to change to a write operation, we can send a start signal again, and then send the address of the read device, without stopping the signal to achieve different address conversion.

Format of data transmitted by IIC

1. Write operations

The main chip sends a start signal first, then a (to determine which chip to write data to), direction (read/write, 0 for write, 1 for read). A response (to determine whether the device exists or not) is then transmitted. After the data is transmitted, there is a response (to determine whether the data has been received or not) before the next data is transmitted. Each time a piece of data is transmitted, the receiver receives a response signal, and when the data is sent, the main chip sends a stop signal.

White background: Master → Slave. Gray background: Slave → Master.

2. Read operation

The main chip first issues a start signal, then a device address (to determine which chip is reading from), direction (read/write, 0 for write, 1 for read). A response (to determine whether the device exists or not) is then transmitted. After the data is transmitted, a response (to determine whether the data is accepted or not) is followed by the next data transmission. Each time a piece of data is transmitted, the receiver receives a response signal, and when the data is sent, the main chip sends a stop signal.

White background: Master → Slave. Gray background: Slave → Master

programming

What is big endian in embedded programming? What is a small end?

Big-endian mode: The low byte is stored at the high address, and the high byte is stored at the low address.

Small-endian mode: The high-order byte is stored at the high-order address, and the low-order byte is stored at the low-order address.

STM32 belongs to the little endian mode, for example, u32 temp=0X12345678; Assume that the temp address is 0X2000 0010. So in memory, store becomes:

Address | HEX |0X2000 0010  |  78   56   43  12  |
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Because it is hexadecimal, a number is 0.5 bytes, so 12 represents a byte and 34 represents a byte.

In small-endian mode, the CPU stores operands from low-byte to high-byte, while in big-endian mode, the CPU stores operands from high-byte to low-byte. For example, the 16-bit number 0x1234 is stored in the small-endian CPU memory (assuming it is stored from address 0x4000) as shown in Table 1, while the 16-bit number 0x1234 is stored in the big-endian CPU memory as shown in Table 2.

Table 1 Storage modes of 0x1234 in small-end CPU memory

Memory address Store content
0x4000 0x34
0x4001 0x12

Table 2 Storage modes of 0x1234 in big-end CPU memory

Memory address Store content
0x4000 0x12
0x4001 0x34

The 32-bit width 0x12345678 is stored in the small-endian CPU memory (assuming that it starts at address 0x4000) as shown in Table 3, while the 32-bit width 0x12345678 is stored in the big-endian CPU memory as shown in Table 4.

Table 3 Storage modes of 0x12345678 in the CPU memory of the small end

Memory address Store content
0x4000 0x78
0x4001 0x56
0x4002 0x34
0x4003 0x12

Table 4 Storage mode of 0x12345678 in big-end CPU memory

Memory address Store content
0x4000 0x12
0x4001 0x34
0x4002 0x56
0x4003 0x78

Take the following program as an example:

#include <stdio.h>
struct mybitfields
{
	unsigned short a:4;
	unsigned short b:5;
	unsigned short c:7;
}test;
int main(a)
{
	int i;
	test.a = 2;
	test.b = 3;
	test.c = 0;
	i =*((short*)&test);
	printf("%d\n",i);
	return 0;
}
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The output of the program is 50.

In this example, sizeof (test) =2, we declare a short into three parts, each of which is 4 bits, 5 bits, and 7 bits. The assignment statement I * (short*) &test) converts the above 16-bit memory to short for interpretation.

The binary representation of variable A is 0000000000000010, with the lower four bits being 0010. The binary representation of variable B is 0000000000000011, with the lower five digits being 00011. The binary representation of the variable C is 0000000000000000, with its lower seven bits 0000000.

80×86 machine is the small end (modify partition table should pay attention to) mode, microcontroller generally for the big end mode. The little endian is usually the lowest byte before the highest byte, that is, the lowest byte is at the lower end of the memory address. It can be written in this way (the little endian → the lowest byte → the first byte → the reverse of the normal logical order), so the resultant result is 0000000000110010, that is, 50 in decimal.

Here’s another example

#include <stdlib.h>
#include <stdio.h>
#include <string.h>
int main(a)
{
	unsigned int uiVal_1 = 0x12345678;
	unsigned int uiVal_2 = 0;
	unsigned char aucVal[4] = {0x12.0x34.0x56.0x78};
	unsigned short usVal_1 = 0;
	unsigned short usVal_2 = 0;
	memcpy(&uiVal_2,aucVal,sizeof(uiVal_2));
	usVal_1 = (unsigned short)uiVal_1;// truncate here
	usVal_2 = (unsigned short)uiVal_2;// Truncated here
	printf("usVal_1:%x\n",usVal_1);// Convert back here
	printf("usVal_2:%x\n",usVal_2);// Convert back here
	return 0;

}
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In the small-endian mode, the low-byte address stores the low-byte address, and the high-byte address stores the high-byte address

78/ / lower address
56
34
12/ / high address
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In memory the test machine is small end, address from small to large.

val1:78563412
riVal2:12345678
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The results are as follows:

5678
3412
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How to determine whether a computer processor is big or small?

#include <stdio.h>
int checkCPU(a)
{{union w
		{
			int a;
			char b;
		}c;
		c.a =1;
		return(c.b == 1); }}int main(a)
{
	if(checkCPU())
		printf("Little end \ n");
	else
		printf("The big end \ n");
	return 0;
}
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The processor of the editor is THE NTEL processor, because Intel processors are generally small – end mode, so the output result of the program is: small – end

In the above code, 0 is returned if the processor is a big end; If the processor is a small end, the union is stored in the order that all the members of the union are stored from the lower address. If you can change the code to know whether the CPU reads and writes memory in small end mode or in big end mode, you will be very interested in the interview.

It can also be determined by the address of the pointer. Since on 32-bit computer systems, short takes up two bytes and char takes up one byte, this can be done as follows.

#include <stdio.h>
int checkCPU(a)
{
	unsigned short usData = 0x1122;
	unsigned char*pucData = (unsigned char*)&usData;
	return (*pucData == 0x22);
}
int main(a)
{
	if(checkCPU())
		printf("Little end \ n");
	else
		printf("The big end \ n");
	return 0;
}
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The result of the program output is: small endian

How do I convert the size side?

int swapInt32(int intValue){

    int temp = 0;

    temp = ((intValue & 0x000000FF) < <24)|

           ((intValue & 0x0000FF00) < <8) |

           ((intValue & 0x00FF0000) > >8) |

           ((intValue & 0xFF000000) > >24);
    return temp;
}
/ * short type: * /
unsigned short swapShort16(unsigned short shortValue){

 

return ((shortValue & 0x00FF) < <8) | ((shortValue & 0xFF00) > >8);

}
/ * float type: * /
float swapFloat32(float floatValue){

         typedef union SWAP_UNION{

         float unionFloat;

         int   unionInt;

         }SWAP_UNION;
         
         SWAP_UNION swapUnion;
         swapUnion.unionFloat = floatValue;
         swapUnion.unionInt = swapInt32(  swapUnion.unionInt);

		return     swapUnion.unionFloat;
}
/* Double = double; /*double = double; * /
void swapDouble64(unsigned char *pIn, unsigned char *pOut){

for( int i=0; i<8; i++) pOut[7-i] = pIn[i];

}

int main(a)
{
    int x = 0x12345678;
    int y = swapInt32(x);
    printf("%x\r\n",y);
    return 0;
}
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How to assign the absolute address 0x100000?

(unsigned int*)0x100000 = 1234;
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So what do you do if you want to jump to the absolute address 0x100000?

* ((void (*)( ))0x100000) ();Copy the code

We first cast 0x100000 to a function pointer, that is:

(void(*) ())0x100000
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Then call it again:

* ((void(*) ())0x100000) (); ,Copy the code

Typedefs are a little more intuitive:

typedef void(*)(a) voidFuncPtr;
*((voidFuncPtr)0x100000) ();Copy the code

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