Small knowledge, big challenge! This article is participating in the creation activity of “Essential Tips for Programmers”.

Bus operation and timing

Four phases of bus transmission

  • Application allocation phase. The request is made by the master module (or master device) that needs to use the bus, and the decision is made by the bus arbiter. Grant bus rights for the next transmission cycle to an applicant. This phase can also be subdivided into transport request and bus mediation phases.

  • Addressing phase. The master module that obtains the right to use the bus issues the address of the slave module (or slave device) to be accessed this time and relevant commands, and starts the slave module that participates in this transmission.

  • Transport phase. Master module and slave module for data exchange, one-way or two-way data transmission.

  • End phase. The information about the main module is removed from the system bus and the bus use right is given away.

Synchronous timing mode

  • Unified clock
  • The transmission speed is fast and the bus control logic is simple
  • The validity test of data communication cannot be carried out in time and the reliability is poor

Asynchronous timing mode

  • Timing control is achieved entirely by transmitting mutually restricted “handshake” signals
  • The bus cycle length is variable to ensure reliable information exchange between two components and devices whose working speeds differ greatly
  • Complex, slow

The asynchronous timing mode is divided into two types

  1. Do not interlock: the request is not back to withdraw, back to the request to withdraw
  2. Semi-interlock: request back to withdraw, back to request their own retreat
  3. Full interlock mode: the request is withdrawn only after it is returned, and the return is withdrawn after the request