The article directories

  • One, foreword
  • Two methods to solve cache inconsistency at hardware level (lock on bus + cache consistency protocol)
    • 2.1 Problems: Cache inconsistency
    • 2.2 Solution: Bus lock + cache consistency
      • 2.2.1 Bus locks, which are atomized by locking the bus
      • 2.2.2 Cache consistency protocol: Through cache invalidation, other cpus forcibly read data from main memory
  • Three concepts in concurrent programming
    • 3.1 atomic
      • 3.1.1 Atomicity definition
      • 3.1.2 Atomicity examples
    • 3.2 the visibility
      • 3.2.1 Definition of visibility
      • 3.2.2 Visibility Examples
    • 3.3 order
      • 3.3.1 Definition of orderliness
      • 3.3.2 Example for Ordering (Instruction reordering in a single thread Does not Cause thread safety problems)
      • 3.3.3 Orderliness Example (Instruction rearrangement in multithreading will cause thread safety problems)</