One: assembly instruction format

The basic syntax of the ARM assembler, which is different from the syntax of the GCC assembler, the overall compilation process is shown below;

Two: how is assembly code converted to binary machine code

It’s simple: switch protocols

For example 🌰 🌰 🌰

mov r1,#0xff

1110 00 1 1101 0 0000 0001 000011111111
Copy the code

  • 11–0 bit: operand. If it is an immediate number, fill in the binary value of the immediate number; if it is a universal register, fill in the binary value of the universal register label

  • 15–12 bits: indicates the destination register

  • 19–16 bits: identifies the first source operand register

  • 20: Indicates whether the instruction affects the program status word register. If yes, set it to one, otherwise set it to zero

  • 24 to 21: indicates the type of the instruction. Mov is 1101

  • 25: indicates whether the shifter_operand section stores instant numbers or registers. Set to zero if it is a register, set to one if it is an immediate number.

  • 27 to 26: reserved bits, constant to 00

  • 31~28: conditional mov is not followed by conditions, so it is 1110

Three: assembly basic instructions – convenient access

I will not post the English document here and we will go back to look it up

Instruction type Instruction width instruction
Data operations 16 ADC, ADD, AND, ASR, BIC, CMN, CMP, CPY, EOR, LSL, LSR, MOV, MUL, MVN,NEG, ORR, ROR, SBC, SUB, TST, REV, REVH, REVSH, SXTB, SXTH, UXTB, and UXTH.
Branches 16 B, B, BL, BX, and BLX. Note, no BLX with immediate.
Load-store single 16 LDR, LDRB, LDRH, LDRSB, LDRSH, STR, STRB, STRH.
Load-store multiple 16 LDMIA, POP, PUSH, and STMIA.
Exception generating 16 BKPT stops in debug if debug enabled, fault if debug disabled. SVC faults to the SVCall handler.
Data operations with immediate 32 ADC{S}. ADD{S}, CMN, RSB{S}, SBC{S}, SUB{S}, CMP, AND{S}, TST, BIC{S}, EOR{S}, TEQ, ORR{S}, MOV{S}, ORN{S}, and MVN{S}.
Data operations with large immediate 32 MOVW, MOVT, ADDW, and SUBW. MOVW and MOVT have a 16-bit immediate. This means they can replace literal loads from memory. ADDW and SUBW have a 12-bit immediate. This means they can replace many from memory literal loads.
Bit-field operations 32 BFI, BFC, UBFX, and SBFX. These are bitwise operations enabling control of position and size in bits. These both support C/C++ bit fields, in structs, in addition to many compare and some AND/OR assignment expressions.
Data operations with three registers 32 ADC{S}. ADD{S}, CMN, RSB{S}, SBC{S}, SUB{S}, CMP, AND{S}, TST, BIC{S},EOR{S}, TEQ, ORR{S}, MOV{S}, ORN{S}, and MVN{S}. No PKxxx instructions.
Shift operations 32 ASR{S}, LSL{S}, LSR{S}, RRX {S}, and ROR {S}.
Miscellaneous 32 REV, REVH, REVSH, RBIT, CLZ, SXTB, SXTH, UXTB, and UXTH.Extension instructions same as corresponding v6 16-bit instructions.
Table branch 32 TBB and TBH table branches for switch/case use. These are LDR with shifts and then branch.
Multiply 32 MUL, MLA, and MLS.
Multiply with 64-bit result 32 UMULL, SMULL, UMLAL, and SMLAL
Load-store single 32 LDR, LDRB, LDRSB, LDRH, LDRSH, STR, STRB, STRH, and T variants. PLD and PLI are both hints and so act as a NOP.
Load-store multiple 32 STM, LDM, LDRD, and STRD.
Load-store exclusive 32 LDREX, STREX, LDREXB, LDREXH, STREXB, STREXH, CLREX. Fault if no local monitor. This is IMP DEF. LDREXD and STREXD are not included in this profile.
Branches 32 B, BL, and B. No BLX (1) because always changes state. No BXJ.
System 32 MSR(2) and MRS(2) replace MSR/MRS but also do more. These access the other stacks and also the status registers.CPSIE/CPSID 32-bit forms are not supported. No RFE or SRS.
System 16 CPSIE and CPSID are quick versions of MSR(2) instructions and use the standard Thumb-2 encodings, but only permit use of i and f and not a.
Extended32 32 NOP (all forms), Coprocessor (MCR, MCR2, MCRR, MRC, MRC2, and MRRC), and YIELD (hinted NOP). Note, no MRS(1), MSR(1), or SUBS (PC return link).
Combined branch 16 CBZ and CBNZ (Compare and Branch if register is Zero or Non-Zero).
Extended 16 IT and NOP. This includes YIELD.
Divide 32 SDIV and UDIV. 32/32 divides both signed and unsigned with 32-bit quotient result, no remainder, it can be derived by subtraction. Early out is permitted.
Sleep 16, 32 WFI, WFE, and SEV are in the class of hinted NOP instructions that control sleep behavior.
Barriers 32 ISB, DSB, and DMB are barrier instructions that ensure certain actions have taken place before the next instruction is executed.
Saturation 32 SSAT and USAT perform saturation on a register. They perform the following: Normalize the value using shift test for overflow from a selected bit position, the Q value. Set the xPSR Q bit if so, saturate the value if overflow detected. Saturation refers to the largest unsigned value or the largest/smallest signed value for the size selected.

Common instruction

B instruction

  • The BL instruction jumps out of the label for execution

  • B. lie: Check whether the value of CMP is less than or equal to the execution label. Otherwise, go straight down

  • B. Gwe must be greater than or equal to the execution address

  • B. lt determines that the value of camp above is less than that of the method in the following address, otherwise go straight down

  • B. gt is greater than the execution address

  • Q is equal to the execution address. Otherwise, go down

  • B. If the result of the comparison is unsigned greater than, execute the method in the address, otherwise do not jump

  • The b.HS instruction is to determine whether unsigned is less than

  • The b.ls instruction is to determine whether unsigned is greater than

  • The lo instruction is to determine whether unsigned is greater than or equal to

Ret return

  • mov x0,#0x10 -> x0 = 0x10

  • STR w10,[sp] stores the w10 register value in sp stack space memory

  • STP x0, x1,[sp.#0x10]* : the values of x0 and x1 are stored in sp + 0x10

  • ORR x0, WZR, # 0 x1: x0 = WZR | 0 x1

  • Stur w10,[sp] stores the value of w10 register in SP stack space memory

  • LDR w10,[sp] w10 = the value in the sp stack memory

  • LDP x0, x1,[sp] x0, x1 = values in the memory of the SP stack

Adrp gets a string from base address + offset (global variable)

  • CBZ comparison, if zero, jump;

  • CBNZ: comparison. If it is non-zero, jump.

  • CMP: comparison function For example: CMP OPR1, OPR2. = (OPR1) – (OPR2)

  • CCMP x13, x12, #0x0, ne indicates that x13 and x12 exist simultaneously

16 bit data operation instruction

The name function
ADC ADD with Carry
ADD add
AND And by location. The bitwise here has the same function as the & of and C
ASR (4) find the Arithmetic Shift Right
BIC Bitwise (bitwise) to zero (bitwise) the inverse of one number with another unsigned number
CMN Negative comparison (comparing one number to the binary complement of another number)
CMP Compare (Compare, Compare two numbers and update flags)
cmp(Compare) More instructions
CMP To compare the contents of one register with the contents or immediate numbers of another register. But the results are not stored, just the correct change flags. General CMP after the judgment will jump, usually followed by B instruction!
CPY To COPY the value of one register into another register
EOR Nearly a xor
LSL Logic Shift Left
LSR Logic Shift Right
MOV Register load data, can be used for transfer between registers, can also be used to load immediate numbers
MUL Multiplication (Multiplication)
MVN Load a number of NOT values (take the logical inverse value)
NEG Take the binary complement
ORR Bitwise or
ROR Cycle moves to the right
SBC Subtraction with borrowing
SUB Subtraction (Subtraction)
TST Test (perform bitwise and operation, and update Z based on results)
REV Reverse the byte order in a 32-bit register
REVH Divide a 32-bit register into two (Half)16 bits, reversing the byte order in each 16 bits
REVSH Byte reversal is performed on the lower 16-bit halfword of a 32-bit register, and then signed extension to 32 bits
SXTB The Signed extension of a Byte to 32 bits
SXTH Signed extension of Half to 32 bits
UXTB An Unsigned extension of a Byte to 32 bits
UXTH Unsigned extends Half to 32 bits

16-bit transfer instruction

The name function
B Unconditional transfer (Branch)
B Conditional transfer
BL Transfer and connect (Link). Used to call a subroutine, the return address is stored in the LR
CBZ Compare, transfer if the result is Zero (can only jump to the following instruction)
CBNZ Compare, transfer if the result is Non Zero (can only jump to the following instruction)
IT If-Then

16 bit memory data transfer instruction

The name function
LDR Load a word from memory into a Register
LDRH Load Half a word from memory into a register
LDRB To load bytes from memory into a register
LDRSH A half-word is loaded from memory and stored in a register after being extended with signs
LDRSB Bytes are loaded from memory and stored in a register after being extended with signs
STR To Store a register word by word into storage
STRH To store the lower half word of a register memory into memory
STRB To store the low bytes of a register into memory
LDMIA Load multiple words and increment the base address register after loading
STMIA Stores multiple words and increments the base address register after storage
PUSH Push multiple registers into the stack
POP To pop multiple values from the stack into registers

Other 16-bit instructions

The name function
SVC System Service Call
BKPT Break Point instruction. If debugging is enabled, the system enters the debugging state (shutdown).
NOP No Operation
CPSIE Enable PRIMASK(CPSIE I)/FAULTMASK(CPSIE f) — clear the corresponding bit
CPSID Except PRIMASK(CPSID I)/FAULTMASK(CPSID f) — set the corresponding bit

32-bit data operation instruction

The name function
ADC Carry addition
ADD add
ADDW Wide addition (can add 12 immediate digits)
AND Bitwise and
ASR Arithmetic moves to the right
BIC Bit-clearing (logical sum of a number with another number after inverting one bit)
BFC A section of the reset
BFI A section of the insert
CMN Negative comparison (comparing one number to another number’s complement and updating flag bits)
CMP Compare the two numbers and update the flag bit
CLZ Count the number of leading zeros
EOR The bitwise exclusive or
LSL The logical left
LSR Logic moves to the right
MLA By adding
MLS By reducing
MOVW Put the 16 bits in the bottom 16 bits of the register, the high 16 bits clear 0
MOV Load 16 bits into register immediately (actually the assembler will produce MOVW)
MOVT Put the 16-bit immediate number into the high 16 bits of the register, and the low 16 bits are not affected
MVN Move the complement of a number
MUL The multiplication
ORR Bitwise or
ORN Bitwise or is performed after bitwise inversion of the source operand
RBIT Bit inversion (to express a 32-bit integer in base 2 and rotate it 180 degrees)
REV To reverse a 32-bit integer by bytes
REVH/REV16 Byte inversion is performed on both high and low halfwords of a 32-bit integer
REVSH Byte reversal is performed on the lower half word of a 32-bit integer, which is then extended to 32 bits with signs
ROR The circle moves to the right
RRX Carried logic moves one space to the right (the highest bit is filled with C and does not affect the value of C)
SFBX An arbitrary bit segment is extracted from a 32-bit integer and expanded to a 32-bit integer with signs
SDIV Signed division
SMLAL Signed long multiply and add (multiply two signed 32-bit integers to produce a 64-bit signed product, and add the product to another signed 64-bit integer)
SMULL Signed long multiplication (the product of two signed 32-bit integers produces a 64-bit signed product)
SSAT Signed saturation operation
SBC Subtraction with borrowing
SUB subtraction
SUBW Width subtraction, you can subtract 12 bits immediately
SXTB Byte signed extension to 32 bits
TEQ Tests for equality (performs xOR on two numbers, updates flags but does not store results)
TST Tests (performs bitwise and on two numbers, updates the Z flag but does not store results)
UBFX Unsigned bit segment extraction
UDIV Unsigned division
UMLAL Unsigned long multiply and add (multiply two unsigned 32-bit integers together to produce an unsigned product of 64 bits and add the product to another unsigned 64-bit integer)
UMULL Unsigned long multiplication (the product of two unsigned 32-bit integers produces an unsigned product of 64 bits)
USAT Unsigned saturation operation (but the source operand is signed)
UXTB Bytes are unsigned extended to 32 bits (high 24 bits clear 0)
UXTH Halfword is unsigned extended to 32 bits (high 16 bits clear 0)

32-bit memory data transfer instruction

The name function
LDR Load the word into the register
LDRB Loads bytes into registers
LDRH Load half word into register
LDRSH Load the half-word into the register and then extend it to 32 bits with signs
LDM Loads multiple words from a contiguity of address space into multiple registers
LDRD Loads a double word (64-bit integer) from a continuous address space into 2 registers
STR Stores the words in the register
STRB Stores low bytes in registers
STRH Stores the lower half word in the register
STM Stores the words in several registers into a contiguic address space
STRD Stores a double word consisting of two registers into a contiguous address space
PUSH To push the values of several registers onto the stack
POP Pops the value of several registers from the stack

32-bit transfer instruction

The name function
B Unconditional transfer
BL Transfer and connect (call subroutine)
TBB Table lookup transfers in bytes. Select an 8-bit forward jump address from a byte array and move it
TBH Lookup table transfers in half-word units. Select a 16 – bit forward – jump address from the half – word group and move

Other 32-bit instructions

The name function
LDREX The word is loaded into the register, and a segment of the address marked in the kernel is entered into a mutually exclusive access state
LDREXH The half-word is loaded into the register, and a segment of the address marked in the kernel is entered into a mutually exclusive access state
LDREXB The byte is loaded into the register, and a segment of the address marked in the kernel is entered into a mutually exclusive access state
STREX Check whether the address to be written is in the mutually exclusive access state, and if so, store the words of the register
STREXH Check whether the address to be written is in the mutually exclusive access state, and if so, store the register’s halfword
STREXB Check whether the address to be written is in the mutually exclusive access state, and if so, store the register bytes
CLREX Clear mutex access status markers (previously marked by LDREX/LDREXH/LDREXB) on local processing
MRS Loads the value of the special function register to the general purpose register
MSR Stores the value of a general purpose register to a special function register
NOP No operation
SEV Send the event
WFE Sleep and wake up when an event occurs
WFI Sleep and wake up when an interrupt occurs
ISB Instruction synchronization isolation (with pipelines, MPU, etc.)
DSB Data synchronization isolation (with pipeline, MPU, cache, etc.)
DMB Data store isolation (with pipeline, MPU, cache, etc.)