Anatomy of RISC-V Architecture (1)
CPU basic knowledge introduction:
- Note the distinction between “processor” and “processor Core,” and the concepts of “CPU” and “Core.”
- The terms “processor Core” and “Core” refer to the inner Core of a processor, which is the true processor Core.
- The terms “processor” and “CPU” are often a complete SoC, containing the processor core and other devices or memory.
- In reality, most articles do not strictly follow the difference between the two, often mixed.
- Instruction Set Architecture (ISA) is the soul of CPU. An instruction set, as the name implies, is a set of instructions, and instructions are the smallest unit of the processor to perform operations (such as addition, subtraction, multiplication and division operations or read/write memory data).
- For MCU and MPU interested to find the relevant information.
Instruction Set Architecture (ISA)
Instruction set architecture is sometimes referred to simply as “architecture” or “processor architecture”. With the instruction set architecture, different processor hardware implementations can be used to design processors with different performance. The specific hardware implementation of the processor is called a Microarchitecture.Although different microarchitectural implementations can cause performance and cost differences, software can run completely on any processor that follows the same instruction set architecture implementation without any modifications. Thus, the instruction set architecture can be understood as an abstraction layer, as shown in the figure below.This abstraction layer forms the bridge and interface between the underlying hardware and the software running on it, and is also an important abstraction layer in modern computer processors.
To enable software programmers to write the underlying software, the instruction set architecture is not just a collection of instructions. It also defines the hardware information that any software programmer needs to know, including the supported data types, Memory, register state, addressing mode, and Memory model.
To sum up, the instruction set architecture is the main standard to distinguish different cpus, which is why Intel and AMD have launched dozens of different CPU chip products over the years. Although they come from two different companies, they are still collectively referred to as x86 architecture cpus.Instruction Set architecture is mainly divided into Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC). The main differences between the two are as follows:
CISC contains not only the commonly used instructions of the processor, but also many special instructions that are not commonly used. The number of instructions is large, so it is called complex instruction set.
RISC contains only the commonly used instructions of the processor, and for uncommon operations, multiple commonly used instructions are executed to achieve the same effect. Because the number of instructions is relatively compact, it is called a compact instruction set.
In the early days of cpus, CISC was dominant because it could do more with fewer instructions. However, with the development of instruction set, more and more special instructions are added to CISC instruction set, and many shortcomings of CISC begin to appear. Such as:
80% of the instructions used in the operations of a typical program account for only 20% of all instruction types. In other words, only 20% of the instructions defined by CISC instruction set are frequently used, while 80% are rarely used.
In particular, special instructions that are rarely used make CPU design extremely complicated, greatly increasing the time and area overhead of hardware design.
For these reasons, since the birth of RISC, almost all modern instruction set architectures have chosen to use RISC architecture.
Introduction to 32-bit and 64-bit architectures:
In addition to CISC and RISC, the number of bits in the processor instruction set architecture is an important concept. Generally speaking, the bit of processor architecture refers to the width of the universal register, which determines the size of the addressing range and the strength of the data computing capability. For example, a processor with 32-bit architecture has a universal register width of 32 bits, an addressable range of 232 bytes, or 4GB of addressable space, and an operation instruction that can operate on 32 bits of operands. The width of the processor’s instruction set architecture has no relation to the encoding length of the instructions. This is not to say that 64-bit architectures have instructions that are 64 bits long (a common misconception). In theory, the shorter the encoding length of the instruction itself, the better, because it saves code storage space. Thus, even in 64-bit architectures, 16-bit encoding instructions abound, and 64-bit encoding instructions are rarely seen.
To sum up, without considering any actual cost and implementation technology, in theory:
The width of the general-purpose register, that is, the number of bits in the instruction set schema, is the better, as this leads to greater addressing range and greater computing power.
The shorter the length of the instruction code, the better, because it saves more code storage space.
Common schema bits are 8, 16, 32, and 64 bits. Early single-chip microcomputer to 8-bit and 16-bit, such as the well-known 8051 single-chip microcomputer is the use of a wide range of 8-bit architecture.
Risc-v architecture brief background:
Risc-v architecture was mainly invented by Professor Krste Asanovic, Andrew Waterman, Yunsup Lee and other developers at the University of California, Berkeley in 2010. And it has the backing of David Patterson, the great guru of computer architecture. The reason the Berkeley developers invented a new instruction set architecture, rather than using mature x86 or ARM architectures, was that these architectures had become extremely complex and cumbersome over the years, and had costly patent and architecture licensing issues. And modifying RTL code for ARM processors is not supported, while source code for x86 processors is simply not available. Other open source architectures (such as SPARC, OpenRISC) have more or less problems (you can check them out if you are interested). The idea of computer architecture and instruction set architecture had been well developed for decades, but a research institution like Berkeley could not choose a suitable instruction set architecture for its use. Berkeley professors and developers decided to invent a new, simple, open and free instruction set architecture, and risC-V architecture was born.
It was originally designed to support computer architecture research and education, but we now hope it will also become a standard free and open industry implementation architecture.
Risc-v (pronounced risk-five) ISA new instruction set architecture (ISA), “V” contains two meanings, one is that it is the fifth generation of instruction set architecture designed by Berkeley from RISC I; The other is that it represents Variation and Vectors.
Risc-v is unusual not only in that it is a recent instruction set architecture (it came out in the last decade, in 2011, while most other instruction sets are from the 1970s and 1980s), but also in that it is an open source instruction set architecture.
After several years of development, Berkeley developed a complete software tool chain and several open source processor instances for RISC-V architecture, which attracted more and more attention. In 2016, RISC-V Foundation (Foundation) was formally established and started operation. The RISC-V Foundation is a non-profit organization responsible for maintaining the standard RISC-V instruction set manuals and architecture documentation and promoting the development of the RISC-V architecture. The RISC-V Foundation is responsible for maintaining the standard RISC-V architecture documentation, compilers and other software tool chains required by cpus, which can be downloaded free of charge by any organization or individual at any time on the RISC-V Foundation website (no registration required). The goals of risC-V architecture are as follows:
A fully open instruction set that can be used freely by any academic institution or commercial organization.
Become a truly suitable hardware implementation and stable standard instruction set.
The goal of the RISC-V Foundation (open, non-profit) is to keep RISC-V stable, develop it slowly and carefully for technical reasons only, and try to make it as popular for hardware as Linux is for operating systems.
Dive into risC-V architecture
Introduction to risC-V modular instruction set
Risc-v’s instruction set is organized in a modular manner, with each module represented by an English letter.
The most basic and only mandatory part of risC-V’s instruction set isby I A subset of basic integer instructions represented by letters. Using this subset of integer instructions, a complete software compiler can be implemented. Other instruction subset parts are optional modules, representative modules include M/A/F/D/C/P, as shown below:Excerpted from RISC-V architecture and embedded development quick starter Hu Zhenbo
Excerpted from The contents of The RISC-V Instruction Set Manual Volume I: Unprivileged ISA (RISC-V Non-privileged Architecture Document)
In addition, “IMAFD”, also known as a “universal” combination, is denoted by the English letter G. Therefore, RV32G indicates RV32IMAFD, and RV64G indicates RV64IMAFD. To improve code density, the RISC-V architecture also provides an optional subset of “compress” instructions, denoted by the English letter C. The instruction encoding length of the compression instruction is 16 bits, while the length of the normal uncompressed instruction is 32 bits.
Risc-v is unusual in addition to being recent and open source, but it is modular, unlike almost all previous isAs. At its heart ISA basic ISA called RV32I that runs a complete software stack. RV32I is fixed and will never change. This provides a stable target for compiler writers, operating system developers, and assembly language programmers. Modularity comes from optional standard extensions that the hardware may or may not include depending on the needs of the application. This modular nature allows RISC-V to be compact and low-power, which can be critical for embedded applications. Once the RISC-V compiler knows what extensions are included on the current hardware, it can generate the best code for the current hardware conditions. The convention is to append the extension letter to the instruction set name as an indication. For example, RV32IMFD adds extensions for multiplication (RV32M), single precision floating point (RV32F), and double precision floating point (RV32D) to the base instruction set (RV32I). They are still optional and will not be a necessary part of all future implementations as they are in incremental ISA. The traditional approach to computer architecture is incremental ISA, where the new processor must implement not only the new ISA extension, but also all the past extensions. Find relevant information if you are interested.
Even the instruction format provides some indication that risC-V’s more compact ISA design can improve the performance to power ratio. First of all, the instructions are onlySix kinds of formatAnd all instructions are 32 bits long, which simplifies instruction decoding. Used for register-register operationsRInstruction for short immediate count and fetch load operationType ICommand used to access the store operation“S”Instruction for conditional jump operationsType BInstruction for long immediate numbersUInstruction and for unconditional jumpJ typeThe instructions. As shown below:
• The embedded architecture supports only 32-bit architectures. This embedded architecture is not supported in 64 or 128-bit architectures. That is, only RV32E, but no RV64E.
• The use of a subset of compression instructions (represented by the letter C), RV32EC, is recommended in embedded architectures to increase the code density of concern in embedded systems.
• A subset of floating-point instructions is not supported in embedded architectures. If you need to choose to support a subset of floating-point instructions (F or D), you must use a non-embedded architecture (RV32I rather than RV32E).
• Embedded architecture only supports Machine Mode and User Mode, not other privileged modes.
• The embedded architecture only supports direct physical address management, not virtual addresses.
In addition to the above modules, there are several modules such as L, B, P, V, and T. Most of these extensions are still being refined and defined and have not yet been finalized, so they will not be discussed in detail.
List of generic RV32G and RV64G instruction sets
The above images are excerpted from The RISC-V Instruction Set Manual Volume I: Unprivileged ISA (RISC-V Non-Privileged Architecture Document) -Chapter 24