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X86 interrupt
Interrupt to CPU sends a signal that the CPU from the normal flow of execution to interrupt, let the CPU to perform other instructions, this signal from other CPU or interrupt controller, interrupt a priority, high priority and low priority interrupt at the same time, interrupt controller is responsible for the high priority interrupt to CPU, interrupts were numbered, Different numbers correspond to different events for cpus, such as clock interrupts, network adapter interrupts, and interCPU interrupts. Cpus can choose to shield interrupts from interrupting their own execution flow, but some interrupts cannot be interrupted.
ARM interrupt
Generic Interrupt Controller (GIC) is a unified Interrupt Controller architecture provided by ARM. It defines the Distributor and CPU Interface of the Interrupt Controller on the ARM platform in detail. At present, GICv3 introduces Interrupt Translation Service (ITS) support, while GICv4 introduces locality-specific Peripheral Interrupts (LPIs) transparent transmission.
Starting with GICv2, support for interruption of virtualization hardware expansion. VGIC introduces a vGIC CPU interface and a corresponding hypervisor control interface for each CPU, and VMS can be configured to use the vGIC CPU interface directly. After an insecure physical interrupt is sent to a CPU CORE, the CPU CORE is triggered to fall into EL2 mode and the interrupt handler in the VMM is allowed to run the List Registers over the interrupt handler based on information such as the VMID of the physical interrupt. Configure and send virtual interrupts to the vGIC CPU interface and route to the corresponding vCPU CORE.
