The articles

Swarm Blockchain distributed storage using MacOS stream editor sed IOS using the Flutter module

start

We through a simple CPU architecture diagram, to understand the implementation of the CPU decoding process.

Now let’s briefly introduce the various nouns in the pictures

The name of the	use
A B C D E F	Represents 6 general purpose registers for data that needs to be provisionally stored
ALU	The ARITHMETIC logic unit (ALU) is a specialized place for performing arithmetic and logical operations
PC	The place where a program counter is used to store the next instruction
MAR	Address register
BR	Full name Buffer register
IR	The place where the CPU instruction set is stored
Decoder	decoder
CU	The control unit, where the CPU executes instructions

Get an instruction

Introduction to Assembly Language

Most of the time our code generated in C++ or Java or some other high-level language is first compiled into assembly language. Assembly language can generate a CPU-specific instruction set, which is a machine language composed of a bunch of binary code that can be directly recognized and executed by the CPU.

0000 indicates LOAD. 0001 indicates STORE.

Generates a CPU instruction in assembly language

Let’s look at a piece of assembly code

INC A
Copy the code

This piece of assembly code means to increment register A once.

This assembly code generates a CPU instruction, in binary form as follows

00111100
Copy the code

Usually I use it in hexadecimal form just to make it easier for us to remember

3C
Copy the code

The memory address of the CPU selected instruction

We put 3C, which increments register A, in memory at the address AE00, as shown in the figure below

Then the CPU loads the instruction address AE00 from memory into the PC program counter. Here we assume that register A already has A data number 00000000. For convenience of memory, we still use its hexadecimal form 00H

After obtaining 3C instruction, the program counter will put this instruction into the MAR(Memory Address Register) address register, then the PC program counter +1, so that the program counter PC can load the next Memory address (so that the next instruction or operation can be fetched).

AE00 address in the address register, through the address bus, go to memory to select the address AE00 of the current CPU operation

Fetch the instruction in the address

After the operation address is selected, the control unit sends the read memory address data operation. Then the selected address AE00 passes its own data through the data bus to the BR buffer register in the CPU. Then copy from the BR buffer register to the IR instruction register. The IR instruction register then puts instruction 3C into the decoder. After the decoder is decoded. The decoded instructions enter the control unit CU, and the execution process is as follows

An instruction to

When the INC A instruction (3C) enters the CU control unit, the CU control unit executes the instruction, puts the temporary data 00H in the A general register into the ALU arithmetic and logic unit, and completes the increment in the ALU.

Above is a complete fetching and decoding process.

conclusion

Do a picture a little rough, please forgive me, what is wrong with the above article, can comment below, I will correct in time