0. Can FPGA also be debugged on chip?
One of the biggest advantages of embedded development such as FPGA and STM32 is that more than 90% of the functions can be verified and 90% of the problems can be found in the timing simulation phase. When all simulations are done, the final step: board-level debugging. If the simulation isn’t right, there’s no need to download it to the chip.
STM32 and other microcontroller, using j-Link or ST-link and other debuggers, can carry out online debugging, because C code is executed in sequence, we can insert breakpoints, let the program stop at the position we need, or real-time view the value of some variables, greatly improve the speed of our Debug, improve product development efficiency.
For FPGA, simulation is simulation after all, and can be understood as ideal conditions, and finally our code needs to run on the actual FPGA chip hardware.
So also encounter simulation is normal, the actual download to the board is not normal. There are two reasons for this: 1. Program bugs; 2. Hardware problems. For example, the reset signal in the actual program is low level reset, while the reset button designed in the actual circuit is high level when pressed. In this way, the program will always be in reset state if the button is not pressed.
Of course, this is only the simplest of problems, and there are many other situations in the real development process where simulation does not match the actual operation. So how to find the problem with the fastest speed?
Early FPGA debugging methods usually used logic analyzer, the external, pin connected to the FPGA chip, if you want to see the internal signal, also need to define the signal as the Output leads to the external tube feet were measured, if it is a number of data, it will take up a lot of pin, but a strong point is that such tools support for multiple protocol parsing, You can easily view the packet data of the protocol.
It would be nice if there was a tool that could get the value of the register in real time through the debugger’s JTAG interface, as MCU development does. There is a market where there is demand. FPGA manufacturers also consider the needs of developers and add this function to their products, that is, on-chip Logic Analyzer, just like a Logic Analyzer ELA (Embedded Logic Analyzer) installed in the chip, can monitor the changes of data in real time. You can also set triggering conditions!
Several manufacturers in the FPGA field provide embedded logic analyzers:
- Intel (formerly Altera) SignalTap tool
- AMD (formerly Xilinx) ChipScope tool
- Identify tool of the Microsemi
- Reveal tool for Lattice
These tools are embedded logic analyzers that greatly improve the debugging speed. The principle of such tools is usually to sample the internal signals of FPGA in real time at a preset clock rate and store them temporarily in the INTERNAL RAM of FPGA. When the preset triggering conditions are met, the data stored in the RAM on chip is transmitted to THE PC through JTAG. After receiving the data, the PC displays the data through the upper computer.
Below is the SPI write sequence of ferroelectric memory FM25V05 captured using ChipScope tool:
From the perspective of FPGA learning process, it is necessary to master the use of on-chip logic analyzer before learning I2C and SPI after understanding the basic routines such as water lamp, button and UART, which is very beneficial to code debugging.
I’ve personally used Xilinx and Microsemi tools, and they work pretty well.
Identify Microsemi: Identify Microsemi: identify Microsemi
Blog.csdn.net/whik1194/ar…
This paper mainly introduces the use of ChipScope tool in Xilinx ISE development environment.
1. The Xilinx ChipScope profile
Xilinx’S FPGA on-chip logic analyzer is called ChipScope, which is implemented by inserting IP core, mainly including three IP cores.
- ICON
ICON (Integrated Controller), mainly responsible for communication with JTAG port, supports connection of up to 15 cores, the Core here can be ILA or VIO.
- ILA
ILA (Integrated Logic Analyzer), embedded logic analyzer, can grasp any internal signal, through the setting of triggering conditions, to grasp the waveform for a period of time, the length of time depends on the SIZE of FPGA RAM resources.
- VIO
Virtual Input/Output (VIO), which is input/output, can monitor the FPGA internal signals in real time and provide driving signals to the FPGA module, which is similar to the view of variable values in MCU debugging.
- ATC2
Agilent Trace Core (ATC2) is a specially customized debugging IP core that needs to be used together with the next-generation Agilent logic analyzer, which is rarely used.
Chipscope_pro_sw_cores_ug029.pdf is the official Document of Xilinx. Chipscope_pro_sw_cores_ug029.pdf is the official guide to ChipScope.
Since it is a logic analyzer, it involves the two most important parameters of the logic analyzer: sampling frequency and sampling depth. The sampling frequency of ILA depends on the frequency of the input clock signal, and the sampling depth depends on the RAM size of the FPGA.
2. Create a sample project
Xilinx Spartan-6 XC6SLX9 is used as an example to demonstrate the use of ChipScope. ILA captures CNT real-time data. VIO can control the LED on and off on the upper computer, or select the blinking frequency. Led1 selects the 4th level flashing frequency through VIO, LED2 flips through the rising edge of the trigger signal given by VIO, and LED3 is consistent with the output height of VIO.
Start by creating an ISE base project based on XC6SLX9 and creating a new source file.
The following code does not add ChipScope yet:
module top(
//Inputs
input clk, //50MHz
input rst_n,
//Outputs
output reg led1, // Use VIO to select 4 flicker frequencies
output reg led2, // Control via VIO
output led3 // Control via VIO
);
wire [1:0] level; / / from the VIO
wire trig; // From VIO, the button generates a high pulse signal
wire trig_rise = (trig_reg == 2'b01);
reg [1:0] trig_reg;
reg [26:0] cnt; // View the data changes in ILA
always @ (posedge clk) begin
if(! rst_n) trig_reg <='h0;
else
trig_reg <= {trig_reg[0], trig};
end
always @ (posedge clk) begin
if(! rst_n) cnt <='d0;
else
cnt <= cnt + 1;
end
always @ (posedge clk) begin
if(! rst_n) led1 <='d0;
else begin
/ / level from the VIO
case (level)
0: led1 <= cnt[26];
1: led1 <= cnt[25];
2: led1 <= cnt[24];
3: led1 <= cnt[23];
endcase
end
end
always @ (posedge clk) begin
if(! rst_n) led2 <=0;
else if(trig_rise) // Trig rising edge flipled2 <= ! led2;end
endmodule
Copy the code3. Add ChipScope ICON IP core
Add an IP core source file to the chipScope folder.
Select ICON IP core. The following operations for adding VIO and ILA core are the same.
After the addition, we will enter the configuration interface. Since we have connected two IP cores, ILA and VIO, we need two control ports here:
Viewing the instantiation template:
icon YourInstanceName (
.CONTROL0(CONTROL0), // INOUT BUS [35:0]
.CONTROL1(CONTROL1) // INOUT BUS [35:0]
);
Copy the code4. Add ChipScope ILA IP core
Select the sampling depth. The larger the value, the more FPGA RAM resources are occupied and the longer the sampling time is.
Select collection channels. Here, 32 channels are selected.
Wait until the generation is complete and view the instantiation template:
ila YourInstanceName (
.CONTROL(CONTROL), // INOUT BUS [35:0]
.CLK(CLK), // IN
.TRIG0(TRIG0) // IN BUS [31:0]
);
Copy the code5. Add the ChipScope VIO IP core
Add VIO cores in the same way:
Select 32 inputs for monitoring the value of CNT and 4 outputs for controlling LED.
Set the input to 32 bits and output to 4 bits.
Add ChipScope’s 3 IP cores to the top layer module
module top(
//Inputs
input clk, //50MHz
input rst_n,
//Outputs
output reg led1, // Use VIO to select 4 flicker frequencies
output reg led2, // Control via VIO
output led3 // Control via VIO
);
wire [1:0] level; / / from the VIO
wire trig; // From VIO, the button generates a high pulse signal
wire trig_rise = (trig_reg == 2'b01);
reg [1:0] trig_reg;
reg [26:0] cnt; // View the data changes in ILA
always @ (posedge clk) begin
if(! rst_n) trig_reg <='h0;
else
trig_reg <= {trig_reg[0], trig};
end
always @ (posedge clk) begin
if(! rst_n) cnt <='d0;
else
cnt <= cnt + 1;
end
always @ (posedge clk) begin
if(! rst_n) led1 <='d0;
else begin
/ / level from the VIO
case (level)
0: led1 <= cnt[26];
1: led1 <= cnt[25];
2: led1 <= cnt[24];
3: led1 <= cnt[23];
endcase
end
end
always @ (posedge clk) begin
if(! rst_n) led2 <=0;
else if(trig_rise) // Trig rising edge flipled2 <= ! led2;end
/* Xilinx ChipScope Config */
wire [35:0] CONTROL0;
wire [35:0] CONTROL1;
wire [31:0] TRIG0;
wire [31:0] ASYNC_IN;
wire [3:0] ASYNC_OUT;
assign ASYNC_IN[26:0] = cnt[26:0];
assign level = ASYNC_OUT[1:0];
assign trig = ASYNC_OUT[2];
assign led3 = ASYNC_OUT[3];
assign TRIG0[26:0] = cnt[26:0];
assign TRIG0[28:27] = level[1:0];
assign TRIG0[29] = led1;
assign TRIG0[30] = led2;
assign TRIG0[31] = led3;
icon icon_ut0(
.CONTROL0(CONTROL0[35:0]),
.CONTROL1(CONTROL1[35:0])); ila ila_ut0(.CONTROL(CONTROL0[35:0]),
.CLK(clk),
.TRIG0(TRIG0[31:0])); vio vio_ut0(.CONTROL(CONTROL1[35:0]),
.ASYNC_IN(ASYNC_IN[31:0]),
.ASYNC_OUT(ASYNC_OUT[3:0]));endmodule
Copy the code7. Compile and download
Create a bit file. Open ChipScope and download the bit file.
Downloading a Bit file
Rename the signal, set the trigger signal, or control the VIO output state.
Trig is set to PushButton type and set to high pulse.
Led3 is set to ToggleButton type, that is, press the state to flip once.
8. To summarize
SCM online debugging can set breakpoints, let the program stop, FPGA as long as the clock signal exists, it will always run, so it can not set breakpoints artificially, stop the operation of the code.
Nothing can be perfect, the use of pin external logic analyzer will not occupy any logical resources, can parse protocol messages through the logic analyzer, the disadvantage is that can not view the internal signal; The advantage of using the on-chip logic analyzer is that the internal signal can be viewed in real time and triggering conditions can be set. The disadvantage is that it will occupy the LOGIC resources of the FPGA, such as RAM.
Xilinx’s new generation of integrated development tool Vivado lowest support spartan-7 series OF FPGA chip, because the hand only spartan-6 series of development board, so can not demonstrate the use of ChipScope in Vivado environment, basically the same, the use of similar methods. It’s the same debugging tool, after all.
9. References
Official Xilinx document: chipscope_pro_sw_cores_UG029.pdf
10. Obtain the source code
【 ChipScope 】 to obtain the project source code, based on the black gold AX309-Spartan-6 XC6SLX9 development board.